1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
A trench gate structure is applied to semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor) and a MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor), and is a structure that is particularly advantageous for electric power use. For example, A MOSFET having the trench gate structure has a fast switching speed and has a large electric current capacity, which is characterized by having a withstand voltage of about a few tens of volts to 300 volts. Accordingly, it is used in switching power supply for a portable terminal, a personal computer (PC), and the like.
Regarding a power semiconductor device having such a trench gate structure, an n-channel type trench MOSFET will be described as an example. In the trench MOSFET, for example, on a semiconductor wafer on which an n-type drift layer and a p-type base layer are formed in a layered manner, trenches are formed to penetrate the p-type base layer to reach the n-type drift layer. In each trench, a gate electrode material is filled via a gate insulation film. These elements constitute a trench gate. On the bottom side of the n-type drift layer, a drain electrode is formed via an n+-type drain region.
On the other hand, in the p-type base layer, an n+-type source region and a p+-type region formed adjacent thereto are provided. Furthermore, on a top part thereof, a source electrode is formed. In a conventional MOSFET, for example, generally there is adopted a structure such that n+-type source regions arranged adjacent to a trench gate are formed respectively along a forming direction of the trench, and moreover, p+-type regions are formed between these n+-type source regions (for example, refer to FIG. 6 of U.S. Pat. No. 3,329,707). However, in such a structure, a trench interval is restricted by the widths of the n+-type source region and the p+-type region, so that there is a limitation on narrowing down the trench interval.
On the other hand, along with the advance in miniaturization techniques, it is possible to set a distance between trench gates to 1 μm or shorter. Accordingly, for example, there is suggested a structure such that n+-type source regions and p+-type regions are arranged alternately along the forming direction of a trench between trench gates. In other words, it is a structure such that the trench gates are orthogonal to the alternately arranged n+-type source regions and p+-type regions. For example, U.S. Pat. No. 2,950,688 describes an IGBT in which an element upper part structure as described above is applied. Also, Japanese Patent Laid-open Application No. Hei 9-116139 describes an element structure in which trench gates are arranged so that a length from a source region to an injector region along each trench gate is longer than a shortest distance therebetween.
In the power MOSFET adopting the above-described element upper part structure, when a predetermined voltage is applied to the gate electrode material, an inverted layer is formed in a region of the p-type base layer that is adjacent to the gate insulation film, thereby generating an on-state between the source electrode and the drain electrode. In such a power MOSFET, the occupying ratio of a current path (channel) in an element effective area can be increased by miniaturizing the trench interval. Therefore, it is possible to decrease resistance of the power MOSFET in the on-state.
However, in order to decrease the on-resistance in the above-described arrangement structure of the n+-type source regions and the p+-type regions, the occupying ratio of the n+-type source regions in an element region between the trench gates is needed to be increased. A possible problem in this case includes avalanche destruction. This avalanche destruction is caused by occurrence of a large voltage drop in the p-type base layer in an arbitrary cell due to a breakdown current, which occurs when the power MOSFET changes from on to off immediately after an inductance load is driven.
Specifically, when a parasitic npn bipolar transistor constituted of an n+-type source region/a p-type base layer/an n-type drift layer turns on, a large current flows. In a cell where this parasitic bipolar transistor operates, the withstand voltage is decreased as compared to a cell where it does not operate, so that the current concentrates and flows in this cell, which finally leads to device destruction. In the above-described element upper part structure, widening of the width of the n+-type source region is equal to that a high resistance is arranged on the way of a Hall current in the p-type base layer flowing into the p+-type region when the breakdown occurs in the vicinity of a channel. When this resistance is large, the parasitic npn bipolar transistor can easily turn on, and as a result, the avalanche destruction can easily occur.